Any logic function can be reduced to what is called the "sum of the products" of the input variables. Each product term is the logically ANDed combination of input variables. The "sum" of these product terms are the logically ORed combination of the product terms. Any logic function can be reduced to this form.
Based on the sum of products idea, programmable logic arrays (PLAs) are integrated circuit devices which permit a user to implement any logic function by programming an array of AND gates and an array of OR gates. The two arrays of AND and OR gates are coupled. The programming of the array of AND gates determines the product terms of the function; the programming of the array of OR gates selects which product terms will be ORed together.
FIG. 1 is a diagrammatic illustration of a typical PLA. The PLA has 64 input terminals which are connected to an array 10 of AND logic gates. The array 10 is, in turn, coupled to an array 12 of OR logic gates. Eight output terminals of the OR logic gate array 12 are the output terminals of the PLA. In the exemplary device of FIG. 1, each of the input terminals I.sub.1 -I.sub.64 is coupled to a set of inverters 16 so that each input signal gives rise to true and complementary input signals. These input signals are carried on true and complementary input signal lines 14 and 15, respectively. Each of the true and complementary input signal lines is connectable to each of 96 AND gates 11, which form the array 10 of AND gates. Each AND gate 11 generates a product term of input variables I.sub.1 -I.sub.64 and their complements. The particular variables selected for each product term are determined by the programming of the connections of the input signal lines 14, 15 to the AND gates 11, i.e., whether an AND gate 11 is connected to a particular signal line.
The output terminals of the AND gates 11 are each, in turn, connectable to an input terminal of each of the OR gates 13 of the array 12. Each connection of an input terminal of an OR gate 13 to an output terminal of an AND gate 11 is programmable. If no connection is made to a particular AND gate 11, then that particular product term is missing from the sum of products of the OR gate 13.
Thus, the output signal of each OR gate 13 is independently programmable. Each output function may be the sum of up to 96 product terms, each product term having up to 64 input variables, true and complementary. It should be noted that each of the AND gates 11 and OR gates 13 is a large multi-input logic gate, the AND gate 11 having up to 64 input terminals and the OR gate 13 having up to 96 input terminals.
A typical way of programming the PLA is the use of masks which make the programmable connections desired by the user of the PLA. The programming of the PLA is done by the manufacturer of the PLA according to the user's specifications. Another common form of programming PLAs is the use of fuses for the programmable connection. Fuses permit the user to program the PLA by "blowing" the fuse to disconnect the undesired input connections to the logic gates 11, 13. The remaining connections determine the output functions of the PLA.
A common semiconductor technology for PLAs is bipolar technology in which bipolar transistor circuits implement the PLA in an integrated circuit device. PLAs have been implemented in MOS technology also. MOS transistors of one polarity, such as N-channel or NMOS transistors, are used in the integrated circuit. Being smaller, MOS transistors permit more integration and complexity than do bipolar transistors at comparable costs. As in bipolar technology, MOS transistors act as passive load devices which allows a DC current path for the MOS PLA. While not as high as in a bipolar PLA, the MOS PLA still has fairly high power consumption.
A technology with very low power consumption is complementary MOS, or CMOS. In CMOS technology, a typical logic circuit has an output node located between a pair of active transistors of opposite channel polarity. Each gate of the transistor pair is connected to the same input signal so that a signal turning one transistor on, turns the other off. There is never a DC power path and power consumption is very low in CMOS circuits.
However, PLAs heretofore have not fully been implemented in CMOS technology. In prior art devices the input and output buffer circuits are typically true CMOS circuits, but the arrays of AND and OR gates remain single polarity MOS (typically NMOS) transistor circuits with passive loads discussed above.
An examination of a large multi-input CMOS logic gate reveals why the gate arrays remain in single polarity MOS, rather than complementary MOS (CMOS) technology. FIG. 2 shows a circuit diagram of a 16-input (actually 32-input, since each input signal has its complementary signal) CMOS NAND gate which would be used to implement an AND gate 11 in the array 10. The circuit in FIG. 2 has two groups of transistors, one group 19 of transistors with channels of one polarity and the second group 20 of transistors with channels of opposite polarity. Each transistor of one group is paired with a transistor in the second group so that the gates of the paired transistors receive the same input signal. To show that the transistors of the group 20 have channel regions of opposite polarity to that of the transistors in group 19, the transistors of group 20 have an additional circular symbol representing inversion with the normal symbol of an MOS transistor gate.
From this view of a CMOS NAND gate it can be appreciated that the problems of laying out such a circuit in the semiconductor substrate of an integrated circuit are difficult. Each pair of transistors in groups 19, 20 is connected together. Hence the large number of lines for layout in a large input CMOS logic gate becomes a problem. As the number of input lines increases, the problem correspondingly becomes more and more complicated.
A second problem is that the operational response time of the CMOS NAND gate shown in FIG. 2 is very slow. The string of transistors in group 19 has a very large resistance. Combined with the typical capacitance of such a circuit, the resistance-capacitance time constant of the circuit becomes large and the performance of the circuit is unacceptable.
A large multi-input CMOS NOR gate has the same problems. With these difficulties of layout and performance for a single large multi-input CMOS logic gate, the problem of designing an array of these logic gates for a PLA has prevented the creation of a completely CMOS PLA.
The present invention solves or substantially mitigates these problems. With the present invention, arrays of true CMOS AND and OR logic gates are possible. This permits PLAs with very low power consumption and acceptable response times.